Method and device for improving clock stability

ABSTRACT

A method and device for improving clock stability are provided. The method includes: determining whether a difference between a current sender timestamp (ST) and a current receiver timestamp (RT) is a mutated value; pre-processing the ST and RT, if the difference between the ST and RT is a mutated value; acquiring a service clock according to the pre-processed ST and RT; and sending time division multiplex (TDM) data according to the service clock.. Through the embodiments of the present disclosure, a packet delay variance (PDV) may be smoothed, the impairment of the PDV on clock recovery may be reduced, the quality of the clock recovery may be improved, and the problem of clock synchronization may be solved through the mutation processing on the timestamps.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of priority of Chinese PatentApplication No. 200810211970.0, filed on Sep. 12, 2008, titled “Methodand Device For Improving Clock Stability”, and the benefit of priorityof International Patent Application No. PCT/CN2009/071506, filed on Apr.27, 2009, titled “Method and Device For Improving Clock Stability”. Thecontents of both of these applications are hereby incorporated herein byreference in their entireties.

FIELD OF THE TECHNOLOGY

The present disclosure relates to communication technologies, and moreparticularly to a method and device for improving clock stability.

BACKGROUND OF THE DISCLOSURE

In Circuit Emulation Services over Packet (CESoP), it is a key factorthat influences the system performance to accurately recover a timedivision multiplex (TDM) service clock. For example, if a dedicatedleased line is used between two clients connected by a circuit emulationservice channel of the operator, clock frequencies of TDM services ofthe clients must be recovered precisely at the egress of thepacket-based network. Otherwise, over a long period of time frequencymismatch will result in overflow or read-empty of waiting queue at theegress of the packet-based network and cause slip impairment.

An adaptive approach is a common method for recovering clock, in which areceiving end extracts timing information from timestamps carried inpackets and a packet arrival interval. This approach needs no extrareference clock, and is very suitable for use in a packet-based network.The process for adaptive clock recovery is shown in FIG. 1. In FIG. 1,service adaptation modules are used to complete adaptation between a TDMstream and packets. The service adaptation module at a sending endobtains a clock signal from TDM device to drive a counter to count,encapsulates and sends data in packets when receiving a certain amountof TDM stream data, and meanwhile loads a counter value when the packetsare sent, that is, a timestamp into a packet header. The serviceadaptation module at a receiving end receives the packets, uses thetimestamp to recover a service clock at the sending end, and utilizesthe clock to send the TDM data in the packet load in the form of a bitstream.

To recover the clock both timestamps at the packet sending and receptionare needed, which inevitably introduces packet delay characteristics ofthe packet-based network. The key of the adaptive approach lies in howto effectively filter out the impairment of a packet delay variance(PDV) on the clock recovery so as to precisely recover the clock signalat the sending end.

The prior art provides a method for reducing the impairment of the PDVon the clock recovery. The method is as follows: outputting a writesignal after performing traffic shaping on a received data packet;determining a data amount buffered in a first-in-first-out bufferaccording to the write signal and a read clock output by a digitaloscillator; computing a filter parameter according to the write signaland the determined buffered data amount; and determining the recoveredread clock according to the filter parameter.

However, at least the following problems exist in the prior art:

The prior art reduces the impairment of the PDV on the clock recoverymainly by filtering. However, the change of timestamp intervals at thereceiving end may be caused by various reasons, so that the filteringmethod is hardly suitable for different situations. Especially when acertain packet experiences a large delay in the network, a receivertimestamp (RT) is mutated, which seriously impairs the clock recovery.

SUMMARY OF THE DISCLOSURE

The present disclosure is directed to a method and device for improvingclock stability, so as to improve the stability of clock recovery.

A method for improving clock stability is provided in an embodiment ofthe present disclosure, including: determining whether a differencebetween a current sender timestamp (ST) and a current receiver timestamp(RT) is a mutated value; pre-processing the ST and RT, if the differencebetween the ST and RT is a mutated value; acquiring a service clockaccording to the pre-processed ST and RT; and sending time divisionmultiplex (TDM) data according to the service clock.

A device for improving clock stability is also provided in an embodimentof the present disclosure, including: a determining unit, configured todetermine whether a difference between a current sender timestamp (ST)and a current receiver timestamp (RT) is a mutated value; a processingunit, configured to pre-process the ST and RT according to adetermination result from the determining unit; and a service clockacquiring unit, configured to acquire a service clock according to thepre-processed ST and RT from the processing unit.

An apparatus for improving clock stability is further provided in anembodiment of the present disclosure. The apparatus for improving clockstability is connected to a data receiving apparatus and a data sendingapparatus. The data sending apparatus is configured to send TDM datareceived by the data receiving apparatus according to a service clockacquired by the apparatus for improving clock stability. The apparatusfor improving clock stability includes a determining module, aprocessing module, and a service clock acquiring module, wherein: thedetermining module is configured to determine whether a differencebetween an ST and an RT is a mutated value; the processing module isconfigured to pre-process the ST and the RT according to a determinationresult of the determining module; the service clock acquiring module isconfigured to acquire the service clock according to the ST and the RTpre-processed by the processing module.

In the embodiments of the present disclosure, a PDV may be smoothed, theimpairment of the PDV on the clock recovery may be reduced, the qualityof the clock recovery may be improved, and the problem of clocksynchronization may be solved through the mutation processing on thetimestamps.

BRIEF DESCRIPTION OF THE DRAWINGS

To illustrate technical solutions according to embodiments consistentwith the present disclosure more clearly, the accompanying figures fordescribing the embodiments are introduced briefly in the following.Apparently, the accompanying drawings in the following description aresome embodiments of the present disclosure.

FIG. 1 is a flow chart of adaptive clock recovery;

FIG. 2 is a flow chart of a method for improving clock stabilityaccording to a first embodiment of the present disclosure;

FIG. 3 is a schematic diagram of a mutated value and a non-mutated valueof timestamp differences;

FIG. 4 is a flow chart of a method for improving clock stabilityaccording to a second embodiment of the present disclosure

FIG. 5 is a flow chart of a method for detecting and repairing a mutatedvalue according to an embodiment of the present disclosure;

FIG. 6 is a structural diagram of an device for improving clockstability according to an embodiment of the present disclosure;

FIG. 7 is a structural diagram of a determining unit according to anembodiment of the present disclosure;

FIG. 8 is a structural diagram of a service clock acquiring unitaccording to an embodiment of the present disclosure; and

FIG. 9 is a structural diagram of an apparatus for improving clockstability according to an embodiment of the present disclosure.

DETAILED DESCRIPTION OF THE EMBODIMENTS

The embodiments of the present disclosure will be clearly and fullydescribed below with reference to the accompanying drawings. It isobvious that the embodiments to be described are only a part rather thanall of the embodiments of the present disclosure. All other embodimentsderived by those skilled in the art based on the embodiments of thepresent disclosure described herein without paying any creative effortsfall within the scope of the present disclosure.

An embodiment of the present disclosure provides a method for improvingclock stability, which may recover a service clock through an adaptiveapproach. As shown in FIG. 2, the method includes the following blocks.

In Block s201, it is determined whether a difference between a currentsender timestamp (ST) and a current receiver timestamp (RT) is a mutatedvalue, and if yes, the ST and the RT are pre-processed.

The process for determining whether the difference between the currentST and the current RT (receiver/sender timestamp difference) is amutated value is as follows. An amplitude of a difference between acurrent receiver/sender timestamp difference and an averagereceiver/sender timestamp difference is compared with a predeterminedrange to determine whether the amplitude exceeds the predeterminedrange, and if yes, it is detected whether amplitudes of differencesbetween subsequent N receiver/sender timestamp differences and theaverage receiver/sender timestamp difference exceed the range. Here, Nis a variable and can be flexibly configured according to demands of thealgorithm. If the amplitudes of differences between the subsequent Nreceiver/sender timestamp differences and the average receiver/sendertimestamp difference do not exceed the predetermined range, the currentreceiver/sender timestamp difference is a mutated value. If theamplitude of the difference between the current receiver/sendertimestamp difference and the average receiver/sender timestampdifference does not exceed the predetermined range, the currentreceiver/sender timestamp difference is a non-mutated value. Or, if theamplitude of the difference between the current receiver/sendertimestamp difference and the average receiver/sender timestampdifference exceeds the predetermined range, and the amplitudes ofdifferences between the subsequent N receiver/sender timestampdifferences and the average receiver/sender timestamp difference alsoexceed the predetermined range, the current receiver/sender timestampdifference is a non-mutated value.

The physical meaning of the receiver/sender timestamp difference (RT-ST)is a sum of an actual transmission delay (Delay) of a correspondingpacket and an offset between clocks at receiving and sending ends(offset).

ΔT=RT−ST=Delay+offset

The change of either of the transmission delay (Delay) or the clockoffset (offset) will result in the change of the timestamp difference.The possible reasons for the change of AT may be one or more of thefollowing:

1) A queuing delay change caused by a change of the service load;

2) A retransmission delay change caused by multiple retransmissions in aCarrier Sense Multiple Access/Collision Detect (CSMA/CD) method;

3) A change of a packet transmission path; and

4) An adjustment of the execution time of the clock at the sending end.

The first three cases may result in the change of the packettransmission delay (Delay), while the last case may result in the changeof the offset between the clocks at the receiving and sending ends(offset). Among them, only the first two cases may result in a mutationof the timestamp difference. The mutation of the timestamp differenceindicates a small part of timestamp differences that seriously departfrom the statistical regularity of the large part of timestampdifferences among all timestamp differences. As shown in FIG. 3, thetimestamp difference of the n^(th) packet in the left diagram issignificantly higher than other values, while neighboring values remainsubstantially unchanged. Therefore, the timestamp difference of then^(th) packet in the left diagram is a mutated value. The timestampdifference of the n^(th) packet in the right diagram is also anincreased value, but the subsequent packets all show the statisticalregularity in which the values are increased values. Therefore, thetimestamp difference of the n^(th) packet in the right diagram is not amutated value.

When the difference is a mutated value, the ST and the RT arepre-processed. The pre-processing may be as follows. When the differencebetween the ST and the RT (receiver/sender timestamp difference) is amutated value, the current receiver/sender timestamp differencecorresponding to the current ST and the current RT is replaced with theaverage receiver/sender timestamp difference, and a new averagereceiver/sender timestamp difference is computed according to thereplaced current receiver/sender timestamp difference. The pre-processedST and RT include: the original ST, the original RT, and the new averagereceiver/sender timestamp difference.

In Block s202, a service clock is acquired according to thepre-processed ST and RT. A phase-locked computation is performed on thepre-processed ST, RT, and average receiver/sender timestamp differenceto recover the service clock at the sending end.

In Block s203, TDM data is sent according to the service clock.

In this embodiment of the present disclosure, a packet delay variance(PDV) is smoothed, the impairment of the PDV on the clock recovery isreduced, the quality of the clock recovery is improved, and the problemof clock synchronization is solved through the mutation processing onthe timestamps.

An embodiment, the present disclosure provides a method for improvingclock stability, and the application background thereof is to recover aservice clock by a self-adaptive method. As shown in FIG. 4, the methodincludes the following blocks:

In Block s401, packet data is received, a current RT is recorded, andTDM data and STs (more than one ST) are separated from the packet data.The TDM data, the STs, and the RTs (more than one RT) are respectivelystored in order from small to large STs, with one to one correspondencemaintained among the TDM data, the STs, and the RTs. The STs, the RTs,and the TDM data are correspondingly stored in a timestamp buffer areaand a data buffer area at the receiving end.

In Block s402, a data sending mechanism reads TDM data of a currentpacket from the data buffer area while finishing sending a previous datapacket, and meanwhile, the timestamp buffer area sends the correspondingST and RT to a determining and processing unit.

In Block s403, a mutated value of a difference between the current STand the current RT is detected and repaired. It is determined whetherthe current difference between the ST and the RT is a mutated value, andif yes, the ST and the RT are pre-processed. An amplitude of adifference between a current receiver/sender timestamp difference and anaverage receiver/sender timestamp difference is compared with apredetermined range to determine whether the amplitude exceeds thepredetermined range, and if yes, it is detected whether amplitudes ofdifferences between subsequent N timestamp differences and the averagereceiver/sender timestamp difference exceed the predetermined range. Ifthe amplitudes of differences between the subsequent N timestampdifferences and the average receiver/sender timestamp difference do notexceed the predetermined range, the current receiver/sender timestampdifference is a mutated value. If the amplitude of the differencebetween the current receiver/sender timestamp difference and the averagereceiver/sender timestamp difference is within the predetermined range,or if the amplitude of the difference between the currentreceiver/sender timestamp difference and the average receiver/sendertimestamp difference is not within the predetermined range, but theamplitudes of differences between the subsequent N timestamp differencesand the average receiver/sender timestamp difference all exceed thepredetermined range, the current receiver/sender timestamp difference isa non-mutated value. An average timestamp difference is computedaccording to a determination result.

In Block s404, a service clock is acquired according to thepre-processed ST and RT. A phase locked loop (PLL) receives thepre-processed timestamps, including the STs, the RTs, and the averagereceiver/sender timestamp difference, determines an amplitude of afrequency difference or phase difference between an output clock signaland a received clock signal according to the pre-processed ST and RTreceived, performs smooth filtering on the frequency difference or phasedifference between the output clock signal and the received clock signalto filter out the influence of data change and other unstable factors onthe whole module, performs an inversed phase modulation on the frequencyor phase of the output clock signal according to the frequencydifference or phase difference after smooth filtering, fixates theamplitude of the frequency difference or phase difference between theoutput clock signal and the received clock signal, and recovers theservice clock at the sending end.

In Block s405, the data sending mechanism receives the service clock atthe sending end recovered by the PLL, and is driven to push out a TDMbit stream according to the service clock.

The method for detecting and repairing a mutated value in Block s403 isshown in FIG. 5, and includes the following blocks:

In Block s501, an n^(th) packet timestamp pair including an ST and an RTis received and detected, and a receiver/sender timestamp differenceΔT_(n) of the n^(th) packet timestamp pair is computed.

In Block s502, it is determined whether an amplitude of a differencebetween the receiver/sender timestamp difference ΔT_(n) of the nthpacket timestamp pair and an average receiver/sender timestampdifference ΔT_(average) exceeds a predetermined range, and if yes, Blocks503 is performed; otherwise, Block s507 is performed.

In Block s503, an m^(th) (m=n+N) packet timestamp pair is detected, anda receiver/sender timestamp difference ΔT_(m) of the m^(th) packettimestamp pair is computed.

In Block s504, it is determined whether an amplitude of a differencebetween the receiver/sender timestamp difference ΔT_(m) of the m^(th)packet timestamp pair and the average receiver/sender timestampdifference ΔT_(average) exceeds a predetermined range, and if yes, Blocks505 is performed; otherwise, Block s508 is performed.

In Block s505, an m^(th) (m=m−1) packet timestamp pair is detected.

In Block s506, it is determined whether m is greater than n, and if yes,Block s504 is performed to compute the receiver/sender timestampdifference ΔT_(m) of the m^(th) packet timestamp pair; otherwise, Blocks507 is performed.

In Block s507, it is determined that the receiver/sender timestampdifference ΔT_(n) of the n^(th) packet timestamp pair is a non-mutatedvalue, and an average receiver/sender timestamp difference is computed.

In Blocks s508, it is determined that the receiver/sender timestampdifference ΔT_(n) of the n^(th) packet timestamp pair is a mutatedvalue, and the receiver/sender timestamp difference ΔT_(n) of the n^(th)packet timestamp pair is replaced by the average receiver/sendertimestamp difference.

The method for improving clock stability according to the secondembodiment of the present disclosure may smooth a PDV, reduce theimpairment of the PDV on the clock recovery, improve the quality of theclock recovery, and solve the problem of clock synchronization bydetecting mutated values of packets and performing a mutation processingon the timestamps.

In an embodiment, the present disclosure further provides a device forimproving clock stability. As shown in FIG. 6, the device includes adetermining unit 610, a processing unit 620, a service clock acquiringunit 630, and a data sending unit 640.

The determining unit 610 is configured to analyze timestamps from abuffer area, and determine whether an amplitude of a difference betweena difference between a current ST and a current RT and an averagereceiver/sender timestamp difference exceeds a predetermined range, andif yes, detect whether amplitudes of differences between subsequent Nreceiver/sender timestamp differences and the average receiver/sendertimestamp difference exceed the predetermined range. If the amplitudesof differences between the subsequent N receiver/sender timestampdifferences and the average receiver/sender timestamp difference do notexceed the predetermined range, the difference between the ST and the RTis a mutated value. If the amplitude of the difference between thecurrent receiver/sender timestamp difference and the averagereceiver/sender timestamp difference does not exceed the predeterminedrange or if the amplitude of the difference between the currentreceiver/sender timestamp difference and the average receiver/sendertimestamp difference exceeds the predetermined range, but the amplitudesof differences between the subsequent N receiver/sender timestampdifferences and the average receiver/sender timestamp difference allexceed the predetermined range, the current receiver/sender timestampdifference is a non-mutated value.

The processing unit 620 is configured to pre-process the current ST andthe current RT according to a determination result from the determiningunit 610, compute an average receiver/sender timestamp difference, andupdate the original average receiver/sender timestamp difference.

The service clock acquiring unit 630 is configured to compute thepre-processed ST, RT, and average receiver/sender timestamp difference,and recover a service clock at the sending end. The pre-processed ST andRT are involved in a phase-locked computation so as to recover theservice clock at the sending end. The service clock acquiring unit 630is configured to receive the timestamps, including the ST, the RT, andthe average receiver/sender timestamp difference; determine an amplitudeof a frequency difference or phase difference between an output clocksignal and a received clock signal according to the pre-processedtimestamps received after the mutated value pre-processing; performsmooth filtering on the frequency difference or phase difference betweenthe output clock signal and the received clock signal to filter out theinfluence of data change and other unstable factors on the whole module;perform an inversed phase modulation on the frequency or phase of theoutput clock signal according to the output frequency difference orphase difference; fixate the amplitude of the frequency difference orphase difference between the output clock signal and the received clocksignal, and recover the service clock at the sending end.

The data sending unit 640 is configured to send a TDM bit streamaccording to the clock signal recovered by the service clock acquiringunit 630.

The structure of the determining unit 610 is shown in FIG. 7. Thedetermining unit 610 further includes a receiving subunit 611, adetecting subunit 612, and a determining subunit 613.

The receiving subunit 611 is configured to receive the timestampsincluding an ST and an RT from a data receiving unit 650.

The detecting subunit 612 is configured to detect whether an amplitudeof a difference between a current receiver/sender timestamp differenceand an average receiver/sender timestamp difference is within apredetermined range according to the timestamp pair received by thereceiving subunit 611 and the average receiver/sender timestampdifference stored in the detecting subunit 612, and send a detectionresult to the determining subunit 613.

The determining subunit 613 is configured to determine whether thecurrent receiver/sender timestamp difference is a mutated valueaccording to the detection result from the detecting subunit 612.

The structure of the service clock acquiring unit 630 is shown in FIG.8. The service clock acquiring unit 630 includes a phase discriminationsubunit 631, a filtering subunit 632, and a phase modulation subunit633.

The phase discrimination subunit 631 is configured to receive thepre-processed timestamps, including the ST, the RT, and the averagereceiver/sender timestamp difference, and determine an amplitude of afrequency difference or phase difference between an output clock signaland a received clock signal according to the pre-processed timestampsreceived.

The filtering subunit 632 is configured to perform smooth filtering onthe frequency difference or phase difference between the output clocksignal and the received clock signal from the phase discriminationsubunit 631 to filter out the influence of data change and otherunstable factors on the whole module.

The phase modulation subunit 633 is configured to perform an inversedphase modulation on the frequency or phase of the output clock signalaccording to the frequency difference or phase difference output fromthe filtering subunit 632, fixate the amplitude of the frequencydifference or phase difference between the output clock signal and thereceived clock signal, and recover the service clock at the sending end.

A device for improving clock stability according to an embodiment of thepresent disclosure further includes a data receiving unit 650,configured to receive packet data, record RTs, separate TDM data andSTs, send the TDM data to the data sending unit 640, and send the STsand the RTs to the determining unit 610. The STs, the RTs, and the TDMdata are respectively stored in a timestamp buffer area and a databuffer area correspondingly. The TDM data and the timestamps are storedin order from small to large STs, with one to one correspondencemaintained among the TDM data, the STs, and the RTs. The sortingmechanism can effectively reduce the impairment of packet disorder onthe clock recovery.

An embodiment of the present disclosure further provides an apparatusfor improving clock stability. As shown in FIG. 9, the apparatus forimproving clock stability is connected to a data receiving apparatus anda data sending apparatus. The data sending apparatus is configured tosend TDM data received by the data receiving apparatus according to aservice clock acquired by the device for improving clock stability. Theapparatus for improving clock stability includes a determining module710, a processing module 720, and a service clock acquiring module 730.

The determining module 710 is configured to determine whether adifference between a current ST and a current RT is a mutated value.

The processing module 720 is configured to pre-process the ST and the RTaccording to a determination result from the determining module 710.

The service clock acquiring module 730 is configured to acquire theservice clock according to the ST and the RT pre-processed by theprocessing module 720.

The determining module 710 further includes a receiving sub-module 711,a detecting sub-module 712, and a mutated value determining sub-module713.

The receiving sub-module 711 is configured to receive the ST and the RTfrom the data receiving apparatus.

The detecting sub-module 712 is configured to detect whether anamplitude of a difference between a current receiver/sender timestampdifference and an average receiver/sender timestamp difference is withina predetermined range according to the ST and the RT received by thereceiving sub-module 711 and the average receiver/sender timestampdifference stored in the detecting sub-module 712.

The mutated value determining sub-module 713 is configured to determinewhether the current receiver/sender timestamp difference is a mutatedvalue according to a detection result sent by the detecting sub-module712.

The processing module 720 may further include a difference processingsub-module 721.

The difference processing sub-module 721 is configured to compute anaverage receiver/sender timestamp difference according to adetermination result from the mutated value determining sub-module 713and update the average receiver/sender timestamp difference stored inthe detecting sub-module 712.

Alternatively, the processing module 720 may further include adifference replacing sub-module and an average difference sub-module.

The difference replacing sub-module is configured to replace the currentreceiver/sender timestamp difference by the average receiver/sendertimestamp difference stored in the detecting sub-module 712 when adetermination result from the mutated value determining sub-module 713is that the current receiver/sender timestamp difference is a mutatedvalue.

The average difference sub-module is configured to compute an averagereceiver/sender timestamp difference according to the currentreceiver/sender timestamp difference replaced by the differencereplacing sub-module and update the average receiver/sender timestampdifference stored in the detecting sub-module 712 when the determinationresult from the mutated value determining sub-module 713 is that thecurrent receiver/sender timestamp difference is a mutated value, orcompute an average receiver/sender timestamp difference and update theaverage receiver/sender timestamp difference stored in the detectingsub-module 712 when the determination result from the mutated valuedetermining sub-module 713 is that the current receiver/sender timestampdifference is not a mutated value.

The service clock acquiring module 730 further includes a phasediscrimination sub-module 731, a filtering sub-module 732, and a phasemodulation sub-module 733.

The phase discrimination sub-module 731 is configured to receive thepreprocessed timestamps from the processing module 720, and determine anamplitude of a frequency difference or phase difference between anoutput clock signal and a received clock signal.

The filtering sub-module 732 is configured to perform smooth filteringon the frequency difference or phase difference output from the phasediscrimination sub-module 731.

The phase modulation sub-module 733 is configured to perform an inversedphase modulation on the frequency or phase of the output clock signalaccording to the frequency difference or phase difference output fromthe filtering sub-module 732, and fixate the amplitude of the frequencydifference or phase difference between the output clock signal and thereceive clock signal.

The modules mentioned above may be distributed in one or moreapparatuses. The modules may be integrated into one module, or befurther divided into a plurality of sub-modules.

The apparatus according to the embodiments of the present disclosure maysmooth a PDV, reduce the impairment of the PDV on the clock recovery,improve the quality of the clock recovery, and solve the problem ofclock synchronization by the performing a mutation processing on thetimestamps.

Through the description of the implementations, it is clear to thoseskilled in the art that the present disclosure may be implementedthrough hardware, or through software and a necessary universal hardwareplatform. Based on the above, the technical solutions of the presentdisclosure may be embodied in the form of a software product. Thesoftware product may be stored in a nonvolatile storage media (forexample, CD-ROM, USB flash drive, or removable hard disk) and containseveral instructions configured to instruct a computer device (forexample, a personal computer, a server, or network device) to performthe method according to the embodiments of the present disclosure.

It should be understood by those skilled in the art that theaccompanying drawings are schematic views of the preferred embodiments,and modules or processes in the accompanying drawings may not benecessarily required in the implementation of the present disclosure.

It should be understood by those skilled in the art that, modules in adevice according to an embodiment may be distributed in the device ofthe embodiment as described above, or be correspondingly changed to bedisposed in one or more devices different from this embodiment. Themodules of the embodiments may be integrated into one module, or furtherdivided into a plurality of sub-modules.

The sequence numbers of the embodiments of the present disclosure aremerely for the convenience of description, and do not imply thepreference among the embodiments.

Several specific embodiments of the present disclosure are describedabove, and the present disclosure is not limited thereto. Any variationsthat can be easily thought of by those skilled in the art should fallwithin the scope of the present disclosure.

1. A method for improving clock stability, comprising: determiningwhether a difference between a current sender timestamp (ST) and acurrent receiver timestamp (RT) is a mutated value; pre-processing theST and the RT, if the difference between the ST and RT is a mutatedvalue; acquiring a service clock according to the pre-processed ST andRT; and sending time division multiplex (TDM) data according to theservice clock.
 2. The method of claim 1, further comprising: receivingpacket data, recording the current RT, and separating TDM data and theST from the packet data.
 3. The method of claim 2, wherein theseparating TDM data and the ST from the packet data comprises: storingthe TDM data, STs, and RTs in order from small to large STs, with one toone correspondence maintained among the TDM data, the STs, and the RTs.4. The method of claim 1, wherein determining whether a differencebetween the current ST and the current RT is a mutated value comprises:comparing an amplitude of a difference between the currentreceiver/sender timestamp difference and an average receiver/sendertimestamp difference with a predetermined range to determine whether theamplitude exceeds the predetermined range; if yes, detecting whetheramplitudes of differences between subsequent N receiver/sender timestampdifferences and the average receiver/sender timestamp difference exceedthe range; if the amplitudes of differences between the subsequent Nreceiver/sender timestamp differences and the average receiver/sendertimestamp difference do not exceed the predetermined range, determiningthat the current receiver/sender timestamp difference is a mutated value5. The method of claim 4, wherein the pre-processing the ST and RTcomprises: replacing the current receiver/sender timestamp differencewith the average receiver/sender timestamp difference.
 6. The method ofclaim 1, wherein acquiring a service clock according to thepre-processed ST and RT comprises: determining an amplitude of afrequency difference or phase difference between an output clock signaland a received clock signal according to the pre-processed ST and RT;performing smooth filtering on the frequency difference or phasedifference between the output clock signal and the received clocksignal; performing an inversed phase modulation on a frequency or phaseof the output clock signal according to the frequency difference orphase difference after the smooth filtering; fixating the amplitude ofthe frequency difference or phase difference between the clock signaland the received clock signal, and recovering the service clock at thesending end.
 7. A device for improving clock stability, comprising: adetermining unit, configured to determine whether a difference between acurrent sender timestamp (ST) and a current receiver timestamp (RT) is amutated value; a processing unit, configured to pre-process the ST andRT according to a determination result from the determining unit; and aservice clock acquiring unit, configured to acquire a service clockaccording to the pre-processed ST and RT from the processing unit. 8.The device for improving clock stability of claim 7, wherein thedetermining unit comprises a receiving subunit, a detecting subunit anda determining subunit; the receiving subunit is configured to receivecurrent timestamps comprising an ST and an RT; the detecting subunit isconfigured to detect whether an amplitude of a difference between acurrent receiver/sender timestamp difference and an averagereceiver/sender timestamp difference is within a predetermined rangeaccording to the ST and the RT received by the receiving subunit and theaverage receiver/sender timestamp difference stored in the detectingsubunit and send a detection result to the determining subunit; and thedetermining subunit is configured to determine whether the currentreceiver/sender timestamp difference is a mutated value according to thedetection result from the detecting subunit.
 9. The device for improvingclock stability of claim 8, wherein the processing unit comprises adifference processing subunit, configured to compute an averagereceiver/sender timestamp difference according to the determinationresult from the determining subunit and update the averagereceiver/sender timestamp difference stored in the detecting subunit.10. The device for improving clock stability of claim 8, wherein theprocessing unit comprises: a difference replacing subunit, configured toreplace the current receiver/sender timestamp difference by the averagereceiver/sender timestamp difference stored in the detecting subunitwhen the determination result from the determining subunit is that thecurrent receiver/sender timestamp difference is a mutated value; and anaverage difference subunit, configured to compute an averagereceiver/sender timestamp difference according to the currentreceiver/sender timestamp difference replaced by the differencereplacing subunit and update the average receiver/sender timestampdifference stored in the detecting subunit when the determination resultfrom the determining subunit is that the current receiver/sendertimestamp difference is a mutated value, or compute an averagereceiver/sender timestamp difference and update the averagereceiver/sender timestamp difference stored in the detecting subunitwhen the determination result from the determining subunit is that thecurrent receiver/sender timestamp difference is not a mutated value. 11.The device for improving clock stability of claim 7, wherein the serviceclock acquiring unit comprises: a phase discrimination subunit,configured to receive the pre-processed timestamps and determine anamplitude of a frequency difference or phase difference between anoutput clock signal and a received clock signal according to thepre-processed timestamps received; a filtering subunit, configured toperform smooth filtering on the frequency difference or phase differencebetween the output clock signal and the received clock signal from thephase discrimination subunit; and a phase modulation subunit, configuredto perform an inversed phase modulation on the frequency or phase of theoutput clock signal according to the frequency difference or phasedifference output from the filtering subunit, and fixate the amplitudeof the frequency difference or phase difference between the output clocksignal and the received clock signal.
 12. The device for improving clockstability of claim 7, further comprising a data receiving unit and adata sending unit, wherein: the data receiving unit is configured toreceive packet data, record the current RT, separate TDM data and thecurrent ST, send the TDM data to the data sending unit, and send the STand the RT to the determining unit; and the data sending unit isconfigured to send the TDM data received from the data receiving unitaccording to the service clock acquired by the service clock acquiringunit.
 13. A computer-readable medium having computer usable instructionsstored thereon for execution by a processor to perform a methodcomprising: determining whether a difference between a current sendertimestamp (ST) and a current receiver timestamp (RT) is a mutated value;pre-processing the ST and RT, if the difference between the ST and RT isa mutated value; acquiring a service clock according to thepre-processed ST and RT; and sending time division multiplex (TDM) dataaccording to the service clock.